Senior Principal Firmware Engineering Lead

Date Posted:

2026-07-23



Country:

United States of America



Location:

US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG



Position Role Type:

Onsite



U.S. Citizen, U.S. Person, or Immigration Status Requirements:

Active and transferable U.S. government issued security clearance is required prior to start date.​ U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance​



Security Clearance Type:

DoD Clearance: Secret



Security Clearance Status:

Active and existing security clearance required on day 1

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems.  The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.

We are currently seeking a Senior Principal Firmware Engineer Lead to join our team.

The position is an onsite role, located in McKinney, TX.

What To Expect

• Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi.

• Generate FPGA designs for the following applications: gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.

• Translate system level requirements into FPGA requirements

• Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)

• Lead medium sized teams of FPGA designs and code in VHDL for reliability and maintainability

• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage

• Define schedules for FPGA tasking and drive execution to the planned budget and schedule.

• Identify and manage project risks and opportunities.

• Create complete documentation including requirements, verification plan, and user’s guides

• Lead medium sized teams to success.

• Coach, review, and delegate work to junior engineers.

• Serve as a subject-matter expert within discipline.

• Lead internal and external technical reviews.

• Support customer interactions and relations.

• Contribute to product and technology roadmaps

• Make improvements to processes, systems or products to enhance overall performance

• Engage in personal technical growth and facilitate technical growth in peers and junior engineers.

Qualifications You Must Have

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 10 years of prior relevant experience

• Robust experience with each of the following:

  • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)

  • Experience with Xilinx, Altera and/or Microsemi devices and tools

  • Hands on experience with integration and debug of FPGA/ASIC devices

  • Delivering FPGA/ASIC solutions to system level applications

Qualifications We Value

• One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major.  A suitable degree may be counted as 2 years of work experience.

• FPGA/ASIC design experience in one or more of the following areas:

  • Radar processing techniques

  • Image processing techniques for visual and infrared sensors

  • Embedded systems design using ARM, Microblaze, or Nios processors

  • Gigabit serial interfaces and multi-gigabit transceivers (MGTs)

  • Constrained random verification in UVM using System Verilog

  • Verification utilizing emulation platforms, such as Veloce

  • Experience with High Level Synthesis (HLS)

  • Experience with vector processors and/or GPUs

• Demonstrated ability to lead successful teams.

• Experience managing technical, cost, and schedule risks and opportunities.

• Experience with project management tools such as Earned Value and/or Agile Execution.

• Experience communicating and documenting technical topics and presenting to customers and management.

• Experience leading a program transition from development to production.

• Proposal development experience including basis of estimate generation.

• Experience with intellectual property generation (patents & publications).

• Demonstrated mentorship of junior engineers.

What We Offer

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.

This position offers relocation based on candidate eligibility.

Learn More & Apply Now!

This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://www.state.gov/m/ds/clearances/c10978.htm

North Texas: https://careers.rtx.com/global/en/raytheon-north-texas-location

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As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.

The salary range for this role is 132,400 USD - 251,600 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.

Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.

Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.

This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.

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