Design Verification Manager

We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, you will architect, guide, and execute advanced verification strategies for high-performance, next-generation semiconductor products. 

As a manager, you will bridge the gap between high-level architectural complexity and flawlessly executed silicon. You will be responsible for leading an elite engineering group, driving the adoption of cutting-edge methodology, and ensuring zero-bug tape-outs. If you thrive on solving complex microarchitectural puzzles, scaling high-performing teams, and pushing the boundaries of pre-silicon validation quality, this role offers an unparalleled opportunity to make an industry-wide impact. 

Key Responsibilities 

• Team Leadership & Mentorship: Manage, inspire, and grow a team of high-performing design verification engineers. Foster a culture of technical excellence, continuous learning, and collaborative accountability. 

• Allocating resources effectively across multiple parallel chip/block schedules. 

• Verification Strategy & Architecture: Define global verification strategies, infrastructure, and execution plans for complex SoC and IP blocks. Own the testbench architecture from initial specifications down to structural sign-off. 

• Methodology Champion: Drive standard-setting execution using industry-best paradigms, ranging from advanced functional metric tracking to pioneering automated flows. Lead the team across block, sub-system, and full-chip verification environments. 

• Cross-Functional Collaboration: Align closely with Architecture, RTL Design, Physical Design, and Post-Silicon validation teams to identify coverage gaps, debug system-level failures, and ensure timely tape-out milestones. 

Core Technical Domain Expertise 

The ideal candidate is a hands-on technical authority capable of conducting rigorous code reviews, mentoring senior staff, and charting verification roadmaps across the following pillars: 

• Languages & Frameworks: Deep, expert-level fluency in SystemVerilog and Universal Verification 

• Methodology (UVM) architecture. 

• Formal Verification: Proven track record of leveraging formal methods to definitively 

• mathematically prove block-level assertions and catch deep corner-case bugs. 

• Emulation & Hardware Acceleration: Strategic experience utilizing emulation platforms (e.g., Palladium, Zebu, Veloce) to shift-left software integration and accelerate massive system-level test suites. 

Qualifications 

• Minimum Qualifications: 

• Education: Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field. 

• Verification Experience: 10+ years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification. 

• Leadership Experience: 5+ years of dedicated engineering management or formal team leadership experience directly managing engineering headcount, performance reviews, and project delivery schedules. 

• Proven mastery building scalable UVM-compliant testbenches from scratch. 

Preferred Qualifications: 

• Advanced Education: Master's degree or Ph.D. in Electrical Engineering or Computer Science. 

• AI/ML in Verification: Exposure to, or hands-on experience implementing, Artificial Intelligence and Machine Learning techniques within verification pipelines (e.g., using AI/ML for smart stimulus generation, coverage convergence acceleration, automated bug triage, or regression optimization). 

• Experience with multi-protocol high-speed interfaces (e.g., PCIe Gen6/7, CXL, HBM3, NVLink). 

• Demonstrated capability to manage globally distributed engineering teams.